Sunday, 4 May 2014

Timex contended memory timings, the TS2068 kludge board and EXROM at $4000 - $7FFF (continued)

This is a follow up post explaining the results of my oscilloscope investigation and my theories about how the TS2068 works.

The TS# signal is low most of the time, only going high to allow the SCLD to access the VRAM for drawing the screen. This means most of the time the line driver U5 and bus transceiver U9 are enabled. They're disabled for the SCLD video accesses. These accesses take the form of 16 square wave pulses in succession, then a period with no pulses (TS# low) in the time taken for 12 pulses, for each of the 192 lines on the screen, then no pulses at all for the next 70 lines.

The 2 ROMs and 3 banks of DRAM are selected by signals coming from the SCLD (ROMCS#, EXROM#, CAS1#, CAS2#, CAS3#) so that only one is selected at once, whether to accept a value from the data bus (for a CPU write cycle) or to put a value onto the data bus (for a CPU read cycle). For the CPU to read the video memory, the direction of bus transceiver U9 has to be changed so that data can pass from the SCLD/VRAM data bus onto the CPU data bus. There is an extra read signal coming from the SCLD, also called RD# according to the schematic in the Technical Manual, which drives the direction input on the bus transceiver. This read signal is asserted in the range $4000 - $7FFF. Outside that range the bus transceiver drives in the opposite direction (CPU data bus onto SCLD/VRAM bus).

This scheme falls down when other devices assert the data bus in the range $4000 - $7FFF. Although CAS1# won't be asserted (so that the video memory won't drive a specific value onto the SCLD/VRAM data bus), the bus transceiver U9 will still try to assert the CPU data bus with whatever is on the SCLD/VRAM data bus. The fix used by the Timex engineers was to deassert TS# when accessing cartridge memory or bus expansion memory. This ensures that both U5 and U9 are disabled.

The fix takes the form of a 74LS00 chip U21 and some diode/resistor logic on a mini printed circuit board mounted above the vias for U5. U5 is actually mounted on the mini PCB along with U21 and the board connects to the main PCB through the vias for U5. The SCLD signal TS# connects directly to the mini PCB along with MREQ#, ROSCS# and BE#, and the modified version of TS# is used to drive U5 on the mini PCB and U9 on the main PCB.

Looking at the modified version of TS# on an oscilloscope, the regular groups of 16 pulses coming from the SCLD TS# have a wide voltage swing (from ground to +5V), suggesting the SCLD is built using CMOS logic. The pulses coming from U21 have a lower voltage swing (from ground to a bit less than +5V), because U21 is built using TTL. The modified TS# signal drives two TTL logic devices which will accept both forms of logic high.

The fix doesn't apply when the CPU is accessing EXROM in the range $4000 - $7FFF, so U9 will still try to assert whatever is on the SCLD/VRAM data bus onto the CPU data bus. The EXROM chip will also try to assert the CPU data bus and you have a bus conflict - the value on the data bus can't be guaranteed.

Timex contended memory timings, the TS2068 kludge board and EXROM at $4000 - $7FFF

This was first posted on the World of Spectrum hardware forum.

I haven't seen this documented anywhere yet so I thought I'd share my findings. I've been investigating contended memory timings on the Timex Sinclair 2068, in particular what happens when you page in EXROM or cartridge memory in $4000 - $7FFF.

It appears the Timex SCLD still applies memory contention at these locations when the RAM is paged out. I've written a short program which plays beeps using a machine code routine which steps through $4000 - $7FFF making a memory access at each location during the beep timing loop.

When this program runs it plays the same modulated tone regardless of the setting of port F4 bits 2 and 3. When the program steps through $0000 - $3FFF or $8000 - $FFFF you get a higher, pure tone also regardless of the setting of port F4 bits 0 and 1 or 4 - 7.

So the Timex SCLD pays no attention to bits 2 and 3 in port F4 when applying memory contention; contention is applied whether the CPU is accessing contended video memory or "uncontended" ROM in the EXROM socket or the cartridge port. So we might as well call this "contended ROM".

This solves one other small mystery - the kludge board in every TS2068. Like the dead cockroach it consists of a 74LS00 quad 2-input NAND gate chip; however it is not there to fix I/O contention.

Timex SCLDs can be thought of as a modification of 5C112E ULAs. They have the fixed I/O contention of the 5C112E and the same sync pulse and colour burst timing. You get a nice, centred picture, at the expense of the display not working on some televisions because the colour burst comes too late.

The problem with the SCLD seems to be the tristate signal (TS#) which is used to put the Z80 multiplexed address bus and data bus onto the SCLD/VRAM buses. This signal should go low during memory accesses to $4000 - $7FFF but only when (HOME) RAM is enabled at those locations.

From the design of the kludge circuit it seems that TS# coming from the SCLD goes low at those addresses whether the RAM is switched in or not. The kludge circuit fixes this for the cartridge port and the Bus Expansion unit (BE# signal on the edge connector) but not for the EXROM. Otherwise the CPU would read or write to the VRAM at those addresses as well as the cartridge memory or bus expansion device. For reads there would be a conflict on the bus with two devices trying to assert the bus; for writes both devices would receive the written value.

Curiously the kludge circuit does not fix the problem for the EXROM. Presumably this was because the Timex engineers felt that no-one would ever page EXROM in at $4000 - $7FFF, or at least not usefully. The EXROM chip in the standard machine is only 8K long and is written for $0000-$1FFF. If the EXROM is selected at $4000-$7FFF, it will conflict with the VRAM at the same locations when those locations are read.

The Timex Sinclair 2068 cannot reliably access EXROM between $4000 - $7FFF.

Update:

I need to do a little more investigating, this time with an oscilloscope. I'm pretty sure TS# is low during memory accesses to $4000 - $7FFF with EXROM paged in, but I'm not sure what happens to the VRAM signals RAS1# and CAS1#.

Second update:

I did an investigation using an oscilloscope today. Results will be explained in a follow up post.